A New Approach for Electronic Design Automation of Analog Building Blocks

Abstract

Though transistor technology can be produced in channel length smaller than 20nm, analog circuits cannot be designed with small channel length due to non-idealities. Furthermore, in analog circuit design, the design process is challenging due to non-idealities of transistors. Because of the transistor channel length cannot be selected small in analog circuit design, the important performance criteria as power dissipation and chip occupation area must be optimized. Also, the design process must be shortened in the design of analog circuits. In this work, a new approach is proposed for the design automation of symmetrical operational transconductance amplifier. The transconductance (G(m)) of OTA is obtained for different size of transistors with 0.18 mu m TSMC technology in CADENCE environment and a model of transconductance is realized with neural network. The transistor sizes for the desired transconductance is optimized with genetic algorithm.