Analog Building Blocks Optimization for Low-Pass Filter of IEEE 802.11n Wireless LAN: OTA and CCII

Abstract

The design process of analog circuits is a challenging issue due to the nonidealities. Thus, analog IC design must be automated to shorten the design time and must be optimized to improve the important performance criteria, such as power dissipation, estimated chip occupation area, etc. In this work, a genetic algorithm (GA)-based approach is proposed for the low-pass filter design of IEEE 802.11n Wireless LAN. The performance criteria of OTA and CCII are modeled with an artificial neural network and transistor sizes of those blocks are determined with GA to improve the performance and to satisfy the constraints. The advantage of the proposed methodology is to eliminate infeasible solutions before starting circuit design by modeling the design constraints according to the transistor sizes allowed by production technology. The performance of the proposed method is tested with 0.18-mu m technology in CADENCE environment.