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High Speed Comparator Design for the Implementation of Successive Approximation Register ADC

dc.contributor.authorErsin Alaybeyoglu
dc.date.accessioned2023-02-10T12:35:36Z
dc.date.available2023-02-10T12:35:36Z
dc.date.issued2019
dc.identifier10.1109/ISMSIT.2019.8932893
dc.identifier.issn0
dc.identifier.urihttps://dx.doi.org/10.1109/ISMSIT.2019.8932893
dc.identifier.urihttp://hdl.handle.net/11772/11241
dc.source3rd International Symposium on Multidisciplinary Studies and Innovative Technologies, ISMSIT 2019 - Proceedings
dc.subject-
dc.titleHigh Speed Comparator Design for the Implementation of Successive Approximation Register ADC
dc.typeConference Paper
dc.identifier.volume0
dc.identifier.issue0


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